1. Field of the Invention
The present invention refers to a method for producing a gate structure for an MOS transistor and particularly an MOS transistor whose gate oxide has a ramp-shaped shape between source region and drain region.
2. Description of the Related Art
Basically, the production of a MOS transistor is performed in a known way by generating a gate structure on a channel area later disposed between a source region and a drain region. For generating the gate structure a SiO2 layer (gate oxide) will be generated or deposited as dielectricum, on which a Polysilicon layer will be generated as gate electrode layer.
For certain applications, such as LDMOS transistors, it can be advantageous that the dielectric of the gate electrode, i.e. the gate oxide, has a lower thickness on the source side than on the drain side. This combines the call for a low resistance Ron (i.e. a gate oxide as thin as possible) on the source side, and for a high dielectric strength, i.e. a gate oxide as thick as possible, on the drain side. To realize such a gate oxide, up to now, an “oxide ramp” was provided and, as a result, the alignment of the gate electrode was altered on this ramp. Since this method cannot self-adjust to correct the alignment of the gate electrode, restrictions result due to the limited alignment capabilities of the exposure equipment for structuring the polysilicon layer from which the gate electrode is generated.